Field effect transistor devices having thick gate dielectric layers and thin gate dielectric layers

ABSTRACT

A semiconductor device includes a substrate, a fin arranged on the substrate, a first field effect transistor (FET) comprising a first gate stack disposed over the a portion of the fin, the first gate stack including a polysilicon layer and a silicide material disposed on the polysilicon layer, and an epitaxial material disposed over portions of the fin, the epitaxial material defining source and drain regions of the first FET, and a second effect transistor (FET) comprising a second gate stack disposed over the a portion of the fin, the second gate stack including a metal gate material layer, and an epitaxial material disposed over portions of the fin, the epitaxial material defining source and drain regions of the second FET.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation application of application Ser. No. 13/547,647,filed Jul. 12, 2012, which is incorporated by reference herein.

FIELD OF INVENTION

The present invention relates generally to field effect transistor (FET)devices, and more specifically, to FinFET and Tri-gate FETs.

DESCRIPTION OF RELATED ART

Field effect transistor (FET) devices, such as, for example, FinFETs andTri-gate FETS, include fins disposed on a substrate and gate stacksarranged conformally over the fins. In FinFET devices, the fins areoften capped with a capping material such that the gate stacks contactsopposing sides of the fins. Tri-gate FETs may not include the cappingmaterial such that the gate stacks contact the opposing sides and topsurface of the fins

BRIEF SUMMARY

According to one embodiment of the present invention, a semiconductordevice includes a substrate, a fin arranged on the substrate, a firstfield effect transistor (FET) comprising a first gate stack disposedover the a portion of the fin, the first gate stack including apolysilicon layer and a silicide material disposed on the polysiliconlayer, and an epitaxial material disposed over portions of the fin, theepitaxial material defining source and drain regions of the first FET,and a second effect transistor (FET) comprising a second gate stackdisposed over the a portion of the fin, the second gate stack includinga metal gate material layer, and an epitaxial material disposed overportions of the fin, the epitaxial material defining source and drainregions of the second FET.

According to another embodiment of the present invention, asemiconductor device includes a substrate, a fin arranged on thesubstrate, a first field effect transistor (FET) comprising a first gatestack disposed over the a portion of the fin, the first gate stackincluding a polysilicon layer and a silicide material disposed on thepolysilicon layer, and an epitaxial material disposed over portions ofthe fin, the epitaxial material defining source and drain regions of thefirst FET, a silicide material disposed on the epitaxial material, and aconductive material disposed over the silicide material, a second effecttransistor (FET) comprising a second gate stack disposed over the aportion of the fin, the second gate stack including a metal gatematerial layer, an epitaxial material disposed over portions of the fin,the epitaxial material defining source and drain regions of the secondFET, a silicide material disposed on the epitaxial material, and aconductive material disposed over the silicide material.

Additional features and advantages are realized through the techniquesof the present invention. Other embodiments and aspects of the inventionare described in detail herein and are considered a part of the claimedinvention. For a better understanding of the invention with theadvantages and the features, refer to the description and to thedrawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The subject matter which is regarded as the invention is particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The forgoing and other features, and advantages ofthe invention are apparent from the following detailed description takenin conjunction with the accompanying drawings in which:

FIG. 1 illustrates a perspective view of an exemplary arrangement thatis used in the fabrication of FET devices.

FIG. 2 illustrates a side cut-away view along the line 2 of FIG. 1.

FIG. 3 illustrates a side cut-away view along the line 3 of FIG. 1.

FIG. 4 illustrates a side cut-away view along the line 3 of FIG. 1.

FIG. 5 illustrates the formation of a silicide material.

FIG. 6. illustrates the formation of a dielectric material layer.

FIG. 7 illustrates the resultant structure following a planarizationprocess.

FIG. 8 illustrates the formation of a masking layer.

FIG. 9 illustrates the resultant structure following the removal ofdummy gate structures.

FIG. 10 illustrates the formation of nFET and pFET gate stacks.

FIG. 11 illustrates the resultant structure following a planarizationprocess.

FIG. 12 illustrates the formation of a masking layer.

FIG. 13 illustrates the formation of a silicide material.

FIG. 14 illustrates the removal of the masking layer.

FIG. 15 illustrates the formation of capping layers.

FIG. 16 illustrates the resultant structure following the formation ofsource, drain, and gate contacts.

FIGS. 17-20 illustrate an alternate exemplary method for fabricating FETdevices. In this regard:

FIG. 17 illustrates the resultant structure following the proceduresdescribed above in FIGS. 1-13;

FIG. 18 illustrates the removal of the masking layer and the dummy gatestructures;

FIG. 19 illustrates the formation of nFET and pFET gate stacks; and

FIG. 20 illustrates the resultant structure following a planarizationprocess.

FIGS. 21-27 illustrate another alternate exemplary method forfabricating FET devices. In this regard:

FIG. 21 illustrates the resultant structure following the proceduresdescribed above in FIGS. 1-4 and 6;

FIG. 22 illustrates the resultant structure following processes similarto the processes described above in FIGS. 7-11;

FIG. 23 illustrates the formation of a masking layer followed by theformation of a silicide material;

FIG. 24 illustrates the formation of capping layers;

FIG. 25 illustrates the formation of cavities;

FIG. 26 illustrates the formation of conductive contacts; and

FIG. 27 illustrates the resultant structure following the formation ofconductive contacts.

DETAILED DESCRIPTION

In integrated circuits, it is desirable to fabricate FET devices thatoperate at low voltages (e.g., for processing tasks) and FET devicesthat operate at high voltages (e.g., for input/output tasks) on a commonwafer. In this regard, the FET devices that operate at low voltagesinclude relatively thin gate-dielectric layers while the FET devicesthat operate at relatively high voltages include relatively thickgate-dielectric layers. The exemplary embodiments described below offermethods and resultant structures that include FET devices having thickgate-dielectric layers and FET devices having thin gate-dielectriclayers arranged on a common substrate. The FET devices may includeFinFET and/or Tri-gate FET devices.

FIG. 1 illustrates a perspective view of an exemplary arrangement thatis used in the fabrication of FET devices. The arrangement will includea thick gate-dielectric devices and thin gate-dielectric devicesarranged on a common substrate 100. In the illustrated embodiment thedevices may include both nFET devices and pFET devices. Those skilled inthe art will understand that the methods and resultant structuresdescribed herein may include any arrangement or number of nFET or pFETdevices. The illustrated embodiment includes a substrate 100 that mayinclude, for example, a silicon on insulator (SOI) substrate thatincludes a buried oxide (BOX) layer. Alternatively, the substrate 100may include a bulk silicon material substrate. Fins 102 are arranged onthe substrate 100. The fins 102 may include a silicon material such as,for example Si or SiGe. The fins 102 are capped with a capping layer 104that may include, for example, SiO2. Dummy gate structures 106 arearranged on the substrate 100 and conformally over the fins 102. Thedummy gate structures 106 include a polysilicon layer 108 and a hardmasklayer 110 that may include, for example, an oxide or nitride material.In the illustrated embodiment, the dummy gate structures 106 will beremoved (as described below) to form metallic gates of thingate-dielectric devices. The structure 112 includes a polysiliconstructure 114 and a hardmask layer 116.

The arrangement of FIG. 1 may be fabricated using any suitablefabrication methods including, for example, lithographic patterning andetching processes to form the fins 102. Following the formation of thefins 102, the structures 106 and 112 may be formed by, for example, amaterial deposition and lithographic patterning and etching processes.

FIG. 2 illustrates a side cut-away view along the line 2 (of FIG. 1),and FIG. 3 illustrates a side cut-away view along the line 3 (of FIG.1). The illustrated embodiment includes a layer of oxide material 202(not shown for illustrative purposes in FIG. 1) that is formed overportions of the substrate 100, the fins 102 and the capping layers 104.

The capping layer 104 is shown for illustrative purposes and may beincluded in the fabrication of FinFET devices. Alternatively, thecapping layer 104 may be removed. In this regard, the methods andresultant structures described below would include Tri-gate FET devices.

FIG. 4 illustrates a side cut-away view (along the line 3 of FIG. 1) ofthe resultant structure following the formation of source and drainregions 402. The regions 402 are formed by forming a first set ofspacers 404 adjacent to the dummy gate structures 106 and the structure112. The first set of spacers 404 may include, for example, an oxide ornitride material, and may be formed by, for example, a materialdeposition process followed by an etching process. Following theformation of the first set of spacers 404 the regions 402 are formed by,for example, an epitaxial growth process that grows an epitaxialmaterial such as, for example, Si or SiGe from the exposed portions ofthe fins 102. The epitaxial material may be doped in-situ with dopantsduring the epitaxial process. Following the formation of the regions 402a second set of spacers 406 may be formed using similar methods and/ormaterials as discussed above regarding the first spacers 404. Theregions 402 may be implanted with ions following the growth process ifdesired.

FIG. 5 illustrates the formation of a silicide material 502 in exposedportions of the regions 402. The silicide material 502 may include, forexample, a thin transition metal layer such as, for example, titanium,cobalt, nickel, platinum, or tungsten. The wafer is heated, allowing thetransition metal to react with exposed silicon in the active regions ofthe semiconductor device (e.g., source, drain, gate) forming alow-resistance transition metal silicide. The transition metal does notreact with the insulating material present on the wafer. Following thereaction, any remaining transition metal is removed by selectivechemical etching, leaving silicide contacts in only the active regionsof the device.

FIG. 6 illustrates the formation of a first dielectric material layer602 over exposed portions of the silicide material 502, the spacers 404and 406, the hardmask layers 110 and 116, and the substrate 100.Following the formation of the first dielectric material layer 602, asecond dielectric material layer 604 may be formed over the firstdielectric material layer 602. The first and second dielectric materiallayers 602 and 604 may include, for example, a nitride or an oxidematerial that is formed by, for example, low temperature chemical vapordeposition processes.

FIG. 7 illustrates the resultant structure following a planarizationprocess such as, for example, a chemical mechanical polishing (CMP)process that removes portions of the first and second dielectricmaterial layers 602 and 604, the hardmask layers 110 and 116, and thespacers 404 and 406; to expose portions of the spacers 404 and 406 andthe and the structures 114 and 108.

FIG. 8 illustrates the formation of a masking layer 802. The maskinglayer 802 may include, for example, an oxide or nitride material, and isformed by, for example a material deposition followed by a lithographicpatterning and etching process that patterns the masking layer 802 overportions of the exposed portions of the first dielectric material layer602 and the gate stack 114.

FIG. 9 illustrates the resultant structure following the removal of thedummy gate structures 108 (of FIG. 8) that results in cavities 902 thatare partially defined by the spacers 404. The dummy gate structures 108may be removed by, for example, a wet etching (e.g., tetramethylammoniumhydroxide (TMAH) or hot ammonia) or reactive ion etching (RIE) process.In an alternate exemplary embodiment, if a Tri-gate FET arrangement isdesired, the exposed capping layer 104 may be removed following theremoval of the dummy gate structures 108.

FIG. 10 illustrates the formation of nFET and pFET gate stacks in thecavities 902 (of FIG. 9). In this regard, the masking layer 802 (of FIG.9) is removed. A conformal layer of high K material 1002 such as forexample, a hafnium based oxide material is deposited over exposedportions of the arrangement including the cavities 902. A metallic gatematerial 1004 is formed over the high K material layer 1002, and a layerof gate conductor material 1006 is formed over the metallic gatematerial 1004. The metallic gate material layer 1004 may include, forexample one or more layers of gate metal material such as, for example,a metal gate material stack that includes one or more layers of metalmaterials such as, for example, Al, Ta, TaN, W, WN, Ti, TN, Ru and HfSi,having an appropriate work function depending on whether the device isan NFET or a PFET device. The gate conductor material 1006 may include,for example, aluminum, tungsten, or copper. The layers 1002, 1004 and1006 may be formed by, for example a CVD or plasma enhanced chemicalvapor deposition (PECVD) process.

FIG. 11 illustrates the resultant structure following a planarizationprocess such as, for example a CMP process that removes portions of thelayers 1002, 1004 and 1006 to define an nFET gate stack 1001 and a pFETgate stack 1003. The metallic gate material layer 1004 may includedifferent materials in each device if desired to form an nFET gate stack1001 and/or a pFET gate stack 1003. Though the illustrated embodimentincludes an nFET gate stack 1001 and a pFET gate stack 1003, one ofordinary skill in the art would understand that any number orcombination of arrangements of types of FET devices may be formed in asimilar manner, and are not limited to the exemplary arrangementdescribed herein.

FIG. 12 illustrates the formation of a masking layer 1202. The maskinglayer 1202 may include, for example, an oxide or nitride material, andis formed by, for example a material deposition followed by alithographic patterning and etching process that patterns the maskinglayer 1202 over portions of the exposed portions of the first dielectricmaterial layer 602 and the nFET gate stack 1001 and a pFET gate stack1003.

FIG. 13 illustrates the formation of a silicide material 1302 overexposed portions of the gate stack 114. In this regard, the gate stack114 may have been formed (as shown in FIG. 1) from in-situ dopedpolysilicon material. Alternatively, the gate stack 114 may be, forexample, doped using an ion implantation method following the formationof the masking layer 1202, and prior to the formation of the silicidematerial 1302. The silicide material 1302 may be formed using anysuitable salicidation process.

FIG. 14 illustrates the removal of the masking layer 1202 (of FIG. 13).

FIG. 15 illustrates the formation of capping layers 1502 and 1504. Thecapping layer 1502 may include for example, a nitride material, and thecapping layer 1504 may include, for example, an oxide material.

FIG. 16 illustrates the resultant structure following the formation ofsource, drain, and gate contacts. In this regard, portions of thecapping layers 1502 and 1504, and the dielectric material layer 602 areremoved using, for example, a lithographic patterning and etchingprocess that exposes portions of the silicide materials 502 and 1302 andthe nFET gate stack 1001 and a pFET gate stack 1003. The vias are filledwith a conductive material such as, for example, silver, aluminum, orgold, followed by a planarization process that defines conductivecontacts 1602, 1604, 1606, and 1608. The conductive contacts 1602 arecommunicative with source regions 1601 and drain regions 1603. Theconductive contact 1604 is communicative with the gate stack 114 of thethick gate-dielectric material FET device 1620. The conductive via 1608is communicative with the nFET gate stack 1001 of the thingate-dielectric material FET device 1622 and the conductive via 1606 iscommunicative with the pFET gate stack 1003 of the thin gate-dielectricmaterial FET device 1624.

FIGS. 17-20 illustrate an alternate exemplary method for fabricating FETdevices. FIG. 17 illustrates the resultant structure following theprocedures described above in FIGS. 1-13. In this regard, a silicidematerial 1302 has been formed on the gate stack 114.

Referring to FIG. 18, the masking layer 1202 (of FIG. 17) has beenremoved. Following the removal of the masking layer 1202, the dummy gatestructures 108 (of FIG. 17) are removed resulting in cavities 1802 thatare partially defined by the spacers 404. The dummy gate structures 108may be removed by, for example, a wet etching (e.g., tetramethylammoniumhydroxide (TMAH) or hot ammonia) or reactive ion etching (RIE) process.In an alternate exemplary embodiment, if a Tri-gate FET arrangement isdesired, the exposed capping layer 104 may be removed following theremoval of the dummy gate structures 108.

FIG. 19 illustrates the formation of nFET and pFET gate stacks in thecavities 1802 (of FIG. 18). A conformal layer of high K material 1002such as for example, a hafnium based oxide material is deposited overexposed portions of the arrangement including the cavities 1802. Ametallic gate material 1004 is formed over the high K material layer1002, and a layer of gate conductor material 1006 is formed over themetallic gate material 1004. The metallic gate material layer 1004 mayinclude, for example one or more layers of gate metal material such as,for example, Al, Ta, TaN, W, WN, Ti, TiN, Ru and HfSi, having anappropriate work function depending on whether the device is an NFET ora PFET device. The gate conductor material 1006 may include, forexample, aluminum, tungsten, or copper. The layers 1002, 1004 and 1006may be formed by, for example a CVD or plasma enhanced chemical vapordeposition (PECVD) process.

FIG. 20 illustrates the resultant structure following a planarizationprocess similar to the process shown in FIG. 11 that defines an nFETgate stack 1001 and a pFET gate stack 1003. Following the planarizationprocess, capping layers 1502 and 1504 are formed in a similar manner asshown in FIG. 15, and conductive contacts 1602, 1604, 1606, and 1608 areformed in a similar manner as shown in FIG. 16 that are communicativewith the source regions 1601 and drain regions 1603 of the nFET gatestack 1001, pFET gate stack 1003, and gate stack 114 of the thickgate-dielectric material FET device 1620.

FIGS. 21-27 illustrate an alternate exemplary method for fabricating FETdevices. FIG. 21 illustrates the resultant structure following theprocedures described above in FIGS. 1-4 and 6. In this regard, asilicide material (e.g., silicide material 502 of FIG. 5) has not beenformed in exposed portions of the regions 402, and a first dielectricmaterial layer 602 has been formed over exposed portions of the regions402, the spacers 404 and 406, the hardmask layers 110 and 116, and thesubstrate 100. Following the formation of the first dielectric materiallayer 602, a second dielectric material layer 604 may be formed over thefirst dielectric material layer 602.

FIG. 22 illustrates the resultant structure following processes similarto the processes described above in FIGS. 7-11 resulting in thedefinition of an nFET gate stack 1001 and a pFET gate stack 1003.

FIG. 23 illustrates the formation of a masking layer 1202 followed bythe formation of a silicide material 1302 over exposed portions of thegate stack 114 in a similar manner as discussed above in FIGS. 12-13.

FIG. 24 illustrates the formation of capping layers 1502 and 1504 thatare formed in a similar manner as shown in FIG. 15.

FIG. 25 illustrates the removal of portions of the capping layers 1502and 1504, and the first dielectric material layer 602 that formscavities 2502 that expose portions of the regions 402. Following theformation of cavities 2502, a silicide material 2504 is formed onexposed portions of the regions 402 using similar salicidation methodsas described above. The cavities 2502 are partially defined by thesilicide material 2504, and the capping layers 1502 and 1504.

FIG. 26 illustrates the formation of conductive contacts 2602 that fillthe cavities 2502 (of FIG. 25). The conductive contacts 2602 may beformed from any suitable conductive metal and are formed by, forexample, a CVD or PECVD deposition process followed by a planarizationprocess, such as, for example CMP.

FIG. 27 illustrates the resultant structure following the formation ofconductive contacts 2701, 2703, and 2705 that are communicative with thesource regions 1601 and drain regions 1603 of the nFET gate stack 1001,pFET gate stack 1003, and gate stack 114 of the thick gate-dielectricmaterial FET device 1620.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, element components,and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theembodiment was chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

The flow diagrams depicted herein are just one example. There may bemany variations to this diagram or the steps (or operations) describedtherein without departing from the spirit of the invention. Forinstance, the steps may be performed in a differing order or steps maybe added, deleted or modified. All of these variations are considered apart of the claimed invention.

While the preferred embodiment to the invention had been described, itwill be understood that those skilled in the art, both now and in thefuture, may make various improvements and enhancements which fall withinthe scope of the claims which follow. These claims should be construedto maintain the proper protection for the invention first described.

1. A semiconductor device comprising: a substrate; a fin arranged on thesubstrate; a first field effect transistor (FET) comprising: a firstgate stack disposed over a first portion of the fin, the first gatestack including an oxide capping layer disposed on the first portion ofthe fin, a polysilicon layer disposed on the oxide capping layer, and asilicide material disposed on the polysilicon layer; and an epitaxialmaterial disposed over second portions of the fin, the epitaxialmaterial defining source and drain regions of the first FET; and asecond field effect transistor (FET) comprising: a second gate stackdisposed over a third portion of the fin, the second gate stackincluding a conformal high K layer disposed on the second portion of thefin, a metal gate material layer disposed on the conformal high K layer,and a gate conductor material disposed on the metal gate material layer;and the epitaxial material disposed over fourth portions of the fin, theepitaxial material defining source and drain regions of the second FET.2. The device of claim 1, further comprising a silicide materialdisposed on the epitaxial material.
 3. The device of claim 2, furthercomprising a dielectric material layer disposed over portions of thesilicide material.
 4. The device of claim 3, further comprising acapping material disposed over portions of the first FET, the secondFET, and the dielectric material layer.
 5. The device of claim 4,further comprising conductive vias communicative with portions of thesilicide material of the source and drain regions of the first FET andthe second FET.
 6. The device of claim 1, further comprising aconductive via communicative with the silicide material disposed on thepolysilicon layer of the first FET.
 7. The device of claim 4, whereinthe capping material includes a layer of nitride material and a layer ofoxide material disposed on the layer of nitride material.
 8. The deviceof claim 1, wherein the second FET is a complementary metal oxidesemiconductor (CMOS) pFET device.
 9. The device of claim 1, wherein thesecond FET is a complementary metal oxide semiconductor (CMOS) nFETdevice.
 10. (canceled)
 11. (canceled)
 12. A semiconductor devicecomprising: a substrate; a fin arranged on the substrate; a first fieldeffect transistor (FET) comprising: a first gate stack disposed over afirst portion of the fin, the first gate stack including an oxidecapping layer disposed on the first portion of the fin, a polysiliconlayer disposed on the oxide capping layer, and a silicide materialdisposed on the polysilicon layer; and an epitaxial material disposedover second portions of the fin, the epitaxial material defining sourceand drain regions of the first FET; a silicide material disposed on theepitaxial material; and a conductive material disposed over the silicidematerial; a second field effect transistor (FET) comprising: a secondgate stack disposed over a third portion of the fin, the second gatestack including a conformal high K layer disposed on the second portionof the fin, a metal gate material layer disposed on the conformal high Klayer, and a gate conductor material disposed on the metal gate materiallayer; the epitaxial material disposed over fourth portions of the fin,the epitaxial material defining source and drain regions of the secondFET; a silicide material disposed on the epitaxial material; and aconductive material disposed over the silicide material.
 13. The deviceof claim 12, further comprising a capping material disposed overportions of the first FET and the second FET.
 14. The device of claim12, further comprising a conductive via communicative with the silicidematerial disposed on the polysilicon layer of the first FET.
 15. Thedevice of claim 13, wherein the capping material includes a layer ofnitride material and a layer of oxide material disposed on the layer ofnitride material.
 16. The device of claim 13, wherein the conductive viais partially defined by the capping material.
 17. The device of claim12, wherein the second FET is a complementary metal oxide semiconductor(CMOS) pFET device.
 18. The device of claim 12, wherein the second FETis a CMOS nFET device.
 19. (canceled)
 20. (canceled)